Thermal oxidation is used for various semiconductor fabrication process steps such as forming isolation trench including forming a pad oxide layer and trench oxidation, or forming a thermal oxide layer which serves as a buffer during ion implantation. Thermal oxidation also includes an oxidation process after gate patterning, and includes an oxidation process for forming a capacitor dielectric layer. Thermal oxidation is typically performed in a furnace at a high temperature (800° C. to 1100° C.) of an oxidizing ambient, and can be classified into wet and dry thermal oxidation depending on the oxidizing ambient. During thermal oxidation, a silicon substrate is consumed (0.44 micrometer with respect to every 1 micrometer of growing thermal oxide layer) and a volume expansion occurs (2.2 times the consumed silicon). Such a volume expansion results in the formation of shallow pits in the silicon substrate because of excessive thermal oxidation after trench etching for device isolation.
Unfortunately, thermal oxidation is indispensable for semiconductor fabrication. For example, if thermal oxidation is not performed following gate patterning, the characteristics of a gate oxide layer can be degraded even if defects are not created in a semiconductor substrate. Further, during the formation of a shallow trench isolation (“STI”) structure, if thermal oxidation is not performed following gate patterning, junction leakage currents (N+/P leakage currents) can increase.
FIG. 11 shows the distribution of cumulative junction leakage currents with and/without thermal oxidation. In FIG. 11, a P-type substrate is grounded and a voltage of 2.5V is applied to an N+ area (1015 atoms/cm2). As shown, the characteristics of leakage currents without oxidation was poor as compared to that of leakage currents with oxidation. FIG. 12 shows the degradation of a gate oxide layer without the thermal oxidation process. As can be seen, the gate oxide layer is thinner at the edge of an active region than at other regions.
It is ideal that thermal oxidation proceed with minimal thickness and the silicon substrate be conserved to reduce stress resulting from volume expansion. By contrast, a thicker thermal oxide layer is typically required following the formation of a trench in a substrate. If the thermal oxide layer is not sufficiently thick, a tunneling phenomenon might occur. That is, when a nitride liner is formed in the following process, such a thin thermal oxide layer deteriorates the device characteristics. In other words, impurities are generated from defects at the interfaces between the nitride liner and the thermal oxide layer, or within the thermal oxide layer itself, and they are diffused into a silicon substrate (i.e., trench upper edge) through the thermal oxide layer (“tunneling phenomenon”), degrading device characteristics. Therefore, the thermal oxide layer during the STI technique must have a sufficient thickness to trap the impurities.
In the STI technique, a profile of the trench upper edge is changed according to the degree of thermal oxidation because the amount of consumed silicon is variable to the thickness of the thermal oxide layer. That is, the greater the thickness of the thermal oxide layer is, the worse the profile of the trench upper edge. A thick thermal oxide layer of, for example, 200 Å is formed to prevent impurities from penetrating a trench. As shown in FIG. 13, the profile of the trench upper edge becomes sharp and a gate oxide layer becomes thinner at the edge than at other regions, which makes it hard to form a conformal gate oxide layer. Accordingly, the reliability of the gate oxide layer cannot be ensured. If a strong electric field is applied, the gate oxide layer can be broken down.
In another approach, a thin thermal oxide layer of, for example, 100 Å is formed in the trench so as to reduce consumption of the silicon substrate. As shown in FIG. 14, the profile of the trench upper edge is rounded, which makes it possible to prevent a gate oxide layer from being formed too thinly. As mentioned above, if a nitride liner is formed in the following process, impurities can penetrate a silicon substrate. This is because such a thin thermal oxide layer cannot sufficiently trap the impurities.
For this reason, in the trench isolation technique, a thermal oxide layer formed on a trench sidewall must have a sufficient thickness to trap the impurities.
Therefore, it is inevitable that a semiconductor substrate suffer from defects created by the volume expansion because a thermal oxide layer has to be formed having a sufficient thickness.